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[DDR3]ZQキャリブレーション

ZQキャリブレーションのメモ。

http://alasir.com/reviews/bfg_geforce_7800gs_agp/k4j55323qg.pdf.gz page10

PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR

The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators.
This allows a user to match the driver impedance to the system.
To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss.
The value of the resistor must be six times of the desired output impedance.
For example, a 240ohm resistor is required for an output impedance of 40ohm.
To ensure that output impedance is one sixth the value of RQ(within 10 %),
the range of RQ is 120ohm to 360ohm (20ohm to 60ohm) output impedance.
MF,SEN, RES, CK and /CK are not internally terminated.
CK and /CK will be terminated on the system module using external 1% resisters.
The output impedance is updated during all AUTO REFRESH commands and NOP commands
when a READ is not in progress to compensate for variations in voltage supply and temperature.
The output impedance updates are transparent to the system.
Impedance updates do not affect device operation,
and all data sheet timing and current specifications are met during update.
To guarantee optimum output driver impedance after power-up,
the GDDR3(x32) needs at least 20us after the clock is applied and stable to calibrate the impedance upon power-up.
The user may operate the part with less than 20us, but the optimal output impedance is not guaranteed.
The value of ZQ is also used to calibrated the internal address/command termination resisters.
The two termination values that are selectable during power up are 1/2 of ZQ and ZQ.
The value of ZQ is used to calibrate the internal DQ termination resisters.
The two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ.
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