[NEEK]プログラムメモリ=SSRAM成功構成

System ID Unmatchでハマッタので一からQsys構成作り直し。
SSRAMをプログラムメモリにして、動作成功した構成をメモしておく。
SYSID_DBG_QSYS_SSRAM_OK

pll.c0 = cpu_clk 50MHz(Clock Phase Shift無し)
pll.c1 = ssram_clk 50MHz(Clock Phase Shift = +5ns)

■qsf
set_instance_assignment -name VIRTUAL_PIN ON -to ssram_address_out[0]
set_location_assignment PIN_A2 -to ssram_clk
set_location_assignment PIN_C3 -to ssram_reset_n_out
set_location_assignment PIN_F10 -to ssram_byteenable_n_out[0]
set_location_assignment PIN_F11 -to ssram_byteenable_n_out[1]
set_location_assignment PIN_F12 -to ssram_byteenable_n_out[2]
set_location_assignment PIN_F13 -to ssram_byteenable_n_out[3]
set_location_assignment PIN_F9 -to ssram_chipselect_n_out
set_location_assignment PIN_G13 -to ssram_write_n_out
set_location_assignment PIN_E9 -to ssram_outputenable_n_out
set_location_assignment PIN_F7 -to ssram_begintransfer_n_out
set_location_assignment PIN_E12 -to ssram_address_out[1]
set_location_assignment PIN_A16 -to ssram_address_out[2]
set_location_assignment PIN_B16 -to ssram_address_out[3]
set_location_assignment PIN_A15 -to ssram_address_out[4]
set_location_assignment PIN_B15 -to ssram_address_out[5]
set_location_assignment PIN_A14 -to ssram_address_out[6]
set_location_assignment PIN_B14 -to ssram_address_out[7]
set_location_assignment PIN_A13 -to ssram_address_out[8]
set_location_assignment PIN_B13 -to ssram_address_out[9]
set_location_assignment PIN_A12 -to ssram_address_out[10]
set_location_assignment PIN_B12 -to ssram_address_out[11]
set_location_assignment PIN_A11 -to ssram_address_out[12]
set_location_assignment PIN_B11 -to ssram_address_out[13]
set_location_assignment PIN_C10 -to ssram_address_out[14]
set_location_assignment PIN_D10 -to ssram_address_out[15]
set_location_assignment PIN_E10 -to ssram_address_out[16]
set_location_assignment PIN_C9 -to ssram_address_out[17]
set_location_assignment PIN_D9 -to ssram_address_out[18]
set_location_assignment PIN_A7 -to ssram_address_out[19]
set_location_assignment PIN_A6 -to ssram_address_out[20]
set_location_assignment PIN_B18 -to ssram_address_out[21]
set_location_assignment PIN_C17 -to ssram_address_out[22]
set_location_assignment PIN_C18 -to ssram_address_out[23]
set_location_assignment PIN_G14 -to ssram_address_out[24]
set_location_assignment PIN_B17 -to ssram_address_out[25]
set_location_assignment PIN_H3 -to ssram_data_out[0]
set_location_assignment PIN_D1 -to ssram_data_out[1]
set_location_assignment PIN_A8 -to ssram_data_out[2]
set_location_assignment PIN_B8 -to ssram_data_out[3]
set_location_assignment PIN_B7 -to ssram_data_out[4]
set_location_assignment PIN_C5 -to ssram_data_out[5]
set_location_assignment PIN_E8 -to ssram_data_out[6]
set_location_assignment PIN_A4 -to ssram_data_out[7]
set_location_assignment PIN_B4 -to ssram_data_out[8]
set_location_assignment PIN_E7 -to ssram_data_out[9]
set_location_assignment PIN_A3 -to ssram_data_out[10]
set_location_assignment PIN_B3 -to ssram_data_out[11]
set_location_assignment PIN_D5 -to ssram_data_out[12]
set_location_assignment PIN_B5 -to ssram_data_out[13]
set_location_assignment PIN_A5 -to ssram_data_out[14]
set_location_assignment PIN_B6 -to ssram_data_out[15]
set_location_assignment PIN_C16 -to ssram_data_out[16]
set_location_assignment PIN_D12 -to ssram_data_out[17]
set_location_assignment PIN_E11 -to ssram_data_out[18]
set_location_assignment PIN_D2 -to ssram_data_out[19]
set_location_assignment PIN_E13 -to ssram_data_out[20]
set_location_assignment PIN_E14 -to ssram_data_out[21]
set_location_assignment PIN_A17 -to ssram_data_out[22]
set_location_assignment PIN_D16 -to ssram_data_out[23]
set_location_assignment PIN_C12 -to ssram_data_out[24]
set_location_assignment PIN_A18 -to ssram_data_out[25]
set_location_assignment PIN_F8 -to ssram_data_out[26]
set_location_assignment PIN_D7 -to ssram_data_out[27]
set_location_assignment PIN_F6 -to ssram_data_out[28]
set_location_assignment PIN_E6 -to ssram_data_out[29]
set_location_assignment PIN_G6 -to ssram_data_out[30]
set_location_assignment PIN_C7 -to ssram_data_out[31]

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_chipselect_n_out
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_byteenable_n_out
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_outputenable_n_out
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_write_n_out
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_begintransfer_n_out
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_clk

set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_chipselect_n_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_byteenable_n_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_outputenable_n_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_write_n_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_address_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_reset_n_out
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_begintransfer_n_out
set_instance_assignment -name TSU_REQUIREMENT "6 ns" -from * -to ssram_data_out



■sdc
create_clock -name clkin_50 -period "50MHz" [get_ports clkin_50]
set_clock_groups -group [get_clocks clkin_50] -exclusive

derive_pll_clocks -create_base_clocks

########### Cyclone III NEEK ##########################
set CPU_Clock_ext sysid_debug_qsys_inst|pll|sd1|pll7|clk[0]
set SSRAM_Clock_ext sysid_debug_qsys_inst|pll|sd1|pll7|clk[1]

set_clock_groups -group [get_clocks $CPU_Clock_ext] -exclusive
set_clock_groups -group [get_clocks $SSRAM_Clock_ext] -exclusive

set_output_delay -clock [get_clocks $SSRAM_Clock_ext] -reference_pin [get_ports {ssram_clk}] 2.4 [get_ports {ssram_begintransfer_n_out ssram_byteenable_n_out* ssram_write_n_out ssram_chipselect_n_out ssram_outputenable_n_out ssram_address_out* ssram_data_out*}]
set_input_delay -clock [get_clocks $SSRAM_Clock_ext] -reference_pin [get_ports {ssram_clk}] 4.1 [get_ports {ssram_data_out*}]
set_multicycle_path -from [get_ports {ssram_data_out*} ] -setup -end 2

################# Asynchronous ###########################
# Buttons
set_false_path -from [get_ports {button[*]}]
# Reset
set_false_path -from [get_ports {reset_n}]
# LEDS
set_false_path -to [get_ports {led[*]}]

#################### JTAG ################################
# JTAG Constraints copied directly from TimeQuest Cookbook
#constrain the TCK port
create_clock -name altera_reserved_tck -period "10MHz" [get_ports altera_reserved_tck]
#cut all paths to and from tck
set_clock_groups -group [get_clocks altera_reserved_tck] -exclusive
#constrain the TDI port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]
#constrain the TMS port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]
#constrain the TDO port
set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]

スポンサーサイト
カレンダー
01 | 2012/02 | 03
- - - 1 2 3 4
5 6 7 8 9 10 11
12 13 14 15 16 17 18
19 20 21 22 23 24 25
26 27 28 29 - - -
累積訪問者
現在の訪問者
現在の閲覧者数:
最新記事
最新トラックバック
最新コメント
月別アーカイブ
カテゴリ
プロフィール

bobgosso

Author:bobgosso
FPGAのブログへようこそ!

検索フォーム
RSSリンクの表示
リンク
ブロとも申請フォーム

この人とブロともになる

QRコード
QRコード