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[NEEK][audio]Icarus Verilogバッチ

Icarus Verilog用にバッチ作ってみた。

#!/bin/csh -f

#------------------------------
# auto make batch
#------------------------------
chmod 744 alt_mem_phy_defines.v
chmod 744 alt_mem_ddrx_define.iv
\cp -pr neek_audio/testbench/neek_audio_tb/simulation/submodules/alt_mem_phy_defines.v .
\cp -pr neek_audio/testbench/neek_audio_tb/simulation/submodules/alt_mem_ddrx_define.iv .

#------------------------------
# auto make batch
#------------------------------
echo "iverilog \\" > iverilog.iv
ls -lst neek_audio/simulation/submodules/*.v | sed 's/.* neek_audio/neek_audio/' | sed 's/$/ \\/' > iverilog.sub.v.list
ls -lst neek_audio/simulation/submodules/*.sv | sed 's/.* neek_audio/neek_audio/' | sed 's/$/ \\/' > iverilog.sub.sv.list
echo "neek_audio/testbench/neek_audio_tb/simulation/neek_audio_tb.v" > iverilog.tb
echo "vvp a.out" > iverilog.vvp
echo "gtkwave neek_audio_tb.vcd" > iverilog.gtk

cat iverilog.iv iverilog.sub.v.list iverilog.sub.sv.list iverilog.tb iverilog.vvp iverilog.gtk > go_iverilog

#------------------------------
# go sim
#------------------------------
chmod 744 go_iverilog
./go_iverilog | tee iverilog.log



バッチ実行するとエラーが。


neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1116: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1116: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1117: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1117: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1118: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1118: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1121: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1121: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1122: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1122: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1123: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1123: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1124: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:1124: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:2644: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:2644: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:2645: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:2645: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3485: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3485: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3486: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3486: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3487: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3487: error: invalid module item.
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3488: syntax error
neek_audio/simulation/submodules/neek_audio_ddrc_phy_alt_mem_phy.v:3488: error: invalid module item.
neek_audio/simulation/submodules/alt_mem_ddrx_sideband.v:349: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_tbp.v:474: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_tbp.v:2479: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_tbp.v:3432: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_rdata_path.v:448: warning: Anachronistic use of named begin/end to surround generate sche
mes.
neek_audio/simulation/submodules/alt_mem_ddrx_rdata_path.v:938: warning: Anachronistic use of named begin/end to surround generate sche
mes.
neek_audio/simulation/submodules/alt_mem_ddrx_rank_timer.v:1604: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_input_if.v:283: warning: Anachronistic use of named begin/end to surround generate scheme
s.
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:154: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:155: error: invalid module item.
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:155: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:155: error: Invalid module instantiation
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:155: error: Invalid module instantiation
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:159: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:165: error: invalid module item.
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:166: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:166: error: Invalid module instantiation
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:171: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:171: error: Invalid module instantiation
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:172: error: Invalid module instantiation
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:175: syntax error
neek_audio/simulation/submodules/alt_mem_ddrx_odt_gen.v:182: error: invalid module item.
neek_audio/simulation/submodules/alt_mem_ddrx_ecc_encoder.v:181: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_fifo.v:94: warning: Anachronistic use of named begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_ecc_decoder.v:224: warning: Anachronistic use of named begin/end to surround generate sch
emes.
neek_audio/simulation/submodules/alt_mem_ddrx_ecc_decoder.v:293: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_burst_gen.v:1427: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_cmd_gen.v:1952: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_controller.v:1815: warning: Anachronistic use of named begin/end to surround generate sch
emes.
neek_audio/simulation/submodules/alt_mem_ddrx_arbiter.v:492: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_arbiter.v:733: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_arbiter.v:903: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_arbiter.v:1001: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/alt_mem_ddrx_arbiter.v:1113: warning: Anachronistic use of begin/end to surround generate schemes.
neek_audio/simulation/submodules/i2c_master_byte_ctrl.v:71: Include file timescale.v not found
a.out: Unable to open input file.

GTKWave Analyzer v3.3.39 (w)1999-2012 BSI

Error opening .vcd file 'neek_audio_tb.vcd'.

[NEEK]WM8731で音出力

http://www.ujiya-denshi.com/fpga/0141

上記のページの情報をそのままメモ。

NEEKのLCD daughter boardに載っている,WM8731をI2C経由で初期化する.
FatFsを使って,SDカードをマウント,FATを認識させる.
SDのルートにおいたファイルを開く.
ファイルはあらかじめ48kspsのリニアPCMデータを格納しておく
ファイルからデータを読み出し,DAIに渡す.16bit dataだったので16bit左シフトして渡す.
ファイルの終端に着いたら先頭へseekして無限に繰り返す

[NEEK]NiosII SBTエラー

C:\user\work\neek\audio\software\neek_audio_bsp/HAL/src/alt_main.c:154: warning: Unable to reach (null) (at 0x00018080) from the global pointer (at 0x0200bcac) because the offset (-33504300) is out of the allowed range, -32678 to 32767.



(2013/1/27追記)
おそらく内臓メモリ(0x00018000~0x0001ffff)容量が足りなくて、.bss、.heap、.rodata、.stack
のセクションが配置し切れないって事かな?
内臓メモリを指定していたのを全て外付けFlashに指定変更。
しかし、これでも、指摘されたアドレスが変わっただけで同様のエラーが発生。

C:\user\work\neek\audio\software\neek_audio_bsp/HAL/src/alt_main.c:154: warning: Unable to reach (null) (at 0x06000234) from the global pointer (at 0x0400baf8) because the offset (33507132) is out of the allowed range, -32678 to 32767.


DDR指定になっていた.text、.rwdataも外付けFlash指定にして、結局全てのセクションを
外付けFlashにしたらエラーが消えた。

[NEEK]Qsysで生成したDDRコントローラソースがVerilog、VHDL混在でSim出来ない

表題の通りの状況。
NiosIIからではなく、DDRコントローラを直で制御して、PIXEL FIFOへデータを転送する
モジュールを作りたくて、自作回路+DDRコントローラ+DDRメモリモデルでSimやってみた。

けど、*_ddrc_phy_alt_mem_phy_seq_wrapper.v内の*_ddrc_phy_alt_mem_phy_seq
って回路がVHDLでQsysで生成されてて、Simできない。これは混在Sim可能なSimulatorでしか
先に進めないのか? フリーか格安で混在Sim出来るツールというと、ISE付属のIsimらしいが。
もっと軽いツール無いのか?


#!/bin/csh -f

set do_file = tb_av_ddrc2st.do
set do_opt = "do setup/$do_file; run 100 ms;"

set rtl_list_v = ( \
rtl/tb_av_ddrc2st.v \
rtl/av_ddrc2st.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_arbiter.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_buffer.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_burst_gen.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_controller.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_csr.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_fifo.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_input_if.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_list.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_odt_gen.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_rank_timer.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_rdata_path.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_sideband.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_tbp.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_timing_param.v \
CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_wdata_path.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_alt_mem_ddrx_controller_top.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_controller_phy.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_example_driver.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_example_top.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_ex_lfsr8.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_full_mem_model.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_mem_model.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_phy.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_phy_alt_mem_phy.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_phy_alt_mem_phy_pll.v \
CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_phy_alt_mem_phy_seq_wrapper.v \
)

set rtl_list_sv = ( \
)

set all_alt_v = ( \
quartus/eda/sim_lib/altera_mf.v \
)

#-------------------------------------------------------------------
# work dir
#-------------------------------------------------------------------
\rm -rf work
vlib work


#-------------------------------------------------------------------
# copy
#-------------------------------------------------------------------
\cp CG_2D_qsys/synthesis/submodules/alt_mem_ddrx_define.iv .
\cp CG_2D_qsys/synthesis/submodules/alt_mem_phy_defines.v .

#-------------------------------------------------------------------
# compile
#-------------------------------------------------------------------
foreach hoge ($all_alt_v)
vlog C:/altera/11.1sp1/$hoge
end

foreach hoge ($rtl_list_v)
vlog $hoge
end

#-------------------------------------------------------------------
# sim
#-------------------------------------------------------------------
vsim -t ps tb_av_ddrc2st -do "$do_opt"



上のバッチで実行すると、ModelSim起動後、Loadingで以下のエラーが出る。


# Loading work.CG_2D_qsys_ddrc_phy_alt_mem_phy_seq_wrapper
# ** Error: (vsim-3033) CG_2D_qsys/synthesis/submodules/CG_2D_qsys_ddrc_phy_alt_mem_phy_seq_wrapper.v(365): Instantiation of 'CG_2D_qsys_ddrc_phy_alt_mem_phy_seq' failed. The design unit was not found.
# Region: /tb_av_ddrc2st/ddrc/CG_2D_qsys_ddrc_controller_phy_inst/CG_2D_qsys_ddrc_phy_inst/CG_2D_qsys_ddrc_phy_alt_mem_phy_inst/seq_wrapper
# Searched libraries:
# C:\user\work\neek\CG_2D_lcd_seg_ok\work

[NEEK]Reflesh ConnectionsでUSB Blasterが出ない

ProgrammerでsofはFPGAへダウンロードして、NiosII SBTのRun Configurationの
Target ConnectionタブでReflesh Connectionsを押しても、USB-Blasterが出てこない。

これまでこんな箇所でつまづいた記憶無いんだが。何だろう・・・
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